Accurate analog-to-digital converters are needed which for various applications needing very exact reference voltages having low temperature drift. The design and manufacture of low cost and highly accurate references in digital CMOS processes is difficult. Providing test flow on automatic test equipment (ATE) is another important aspect of manufacturing these electronic devices. Production trimming is expensive and should avoided whenever possible. A typical test procedure includes only two test insertions at two temperatures. The lower temperature is generally not the minimum operating temperature of the device. Thus a trimming procedure does not necessarily provide the most accurate devices. Thus there is a need for electronic devices and methods which provide highest accuracy without trimming and which are easy to implement.
The most accurate approach to achieve stable reference voltages employs the bandgap of bipolar transistors in bandgap reference voltage generators. These reference generators employ the base-emitter voltage (VBE) of bipolar transistors. The base-emitter voltage of a bipolar transistor is not absolutely stable over temperature. Thus measures to stabilize VBE over temperature are required. “Accurate Analysis of Temperature Effects in IC-VBE Characteristics with Application to Bandgap Reference Sources”, IEEE ISSC 1980 by Y. Tsividis provides a very detailed analysis of temperature effects on VBE. “Precision Temperature Sensors in CMOS Technology,” Springer, 2006 by M. Pertis and J. Huijsing provides a briefer and more comprehensible analysis.
The variation of VBE is referred to as curvature of VBE. This generally results from non-linear temperature behavior of the BJT saturation current. A non-linear bias current which exactly cancels out the non-linearity of VBE might be used to compensate or linearize VBE.
The VBE curvature may be compensated according to different principles. These include: VBE linearization with non-linear bias currents or voltages using a temperature dependent gain for a ΔVBE which is added to VBE; and adding piecewise linear voltages to ΔVBE and VBE to compensate the VBE curvature.
FIG. 1 illustrates a simplified schematic of prior art circuit with VBE curvature compensation. A first bipolar transistor Q1 and a second bipolar transistor Q2 with emitter areas having a ratio of 1:N are in two different current paths. Both the bases and collectors of Q1 and Q2 are coupled to ground. This restriction is imposed by some CMOS technologies where bipolar transistors may only be provided with bases and collectors coupled to ground. First resistor R1 and second resistor R2 are coupled in series with the channel of Q1. Resistor R2a is coupled to the channel of Q2. The node between R2a and the emitter of Q2 is VIP. The node between R1 and R2 is VIM. Node VIP is coupled to the positive input of transconductance amplifier OTA. Node VIM is coupled to the inverted or negative input of transconductance amplifier OTA. The output of OTA is coupled to the gate of NMOS transistor N1. N1 is coupled with its channel between power supply VDD and an NWELL resistor R4. NWELL resistor R4 is coupled in series with resistor R3. Resistor R3 is coupled to a common resistor node with resistors R2a and R2. NWELL resistor R4 implements VBE curvature compensation. NWELL resistor R4 has a high temperature coefficient. The change of the voltage drop across R4 is combined with VBE across Q2 and Q2 and the positive temperature coefficients of R3, R2, R2a and R1. The non-linear voltage drop across R4 compensates the non-linearity of VBE. This prior art VBE curvature compensation is easy to design and can be added to existing designs without much modifications. It does not require a lot additional chip area. This prior art contributes an additional process sensitivity to the bandgap reference generator due to the NWELL sheet resistance. This NWELL sheet resistance it fairly difficult to control in known CMOS or BICMOS technologies and renders VBE curvature compensation less robust than required.